1. Field of the Invention
The present invention relates to a highly efficient encoding apparatus, in particular, relates to a highly efficient encoding apparatus suitable for compressing data of a video signal.
2. Description of the Prior Art
Thus far a variety of highly efficient encoding apparatuses for compressing data of a video signal have been proposed. For example, a highly efficient encoding apparatus proposed by the patent applicant as Japanese Patent Laid-open Publication No. SHO 62-92620 discloses a technique for adaptively quantizing data of pictures.
MPEG (Moving Picture Experts Group) has recommended a data compression system with respect to moving pictures. In this recommendation, one frame picture is constructed of 240 lines in the vertical scanning direction, each line being constructed of 352 picture elements, each frame being divided into macro blocks MB constructed of 16 picture elements .times.16 picture elements. Thus, one frame picture is constructed of 22 macro blocks MB in the horizontal scanning direction and 15 macro blocks MB in the vertical scanning direction.
FIG. 1 shows a circuit construction of a highly efficient encoding apparatus using DCT (Discrete Cosine Transform).
A video signal SV is supplied to an A/D converter 81 through a terminal 80. The A/D converter 81 converts the video signal SV into video data DV. The video data DV is supplied to a frame buffer 82.
An address generator 83 forms a write address ADW. The write address ADW is supplied to the frame buffer 82.
The video data DV is written to the frame buffer 82 in accordance with the above mentioned write address ADW. With respect to the video data Dv written to the frame buffer 82, each frame is constructed of 240 lines (that is, 240 picture elements) in the vertical scanning direction, one line being constructed of 352 picture elements.
The address generator 83 forms a read address ADR. The read address ADR is supplied to the frame buffer 82.
The frame buffer 82 reads the video data DV in accordance with the above mentioned read address ADR The video data Dv is read from the frame buffer 82 macro block MB by macro block MB, which is constructed of 16 picture elements .times.16 picture elements. The video data DV which is read macro block MB by macro block MB is supplied to a data generation circuit 84.
The data generation circuit 84 divides each macro block MB into blocks constructed of eight picture elements .times.eight picture elements. Thus, one macro block MB is divided into four blocks.
After video data DV is DCT-processed block by block, it is quantized and converted into a code with a variable length. Thereby, data is compressed and new video data DV0 is formed. After the video data Dv0 is written to a buffer memory 85, it is read in succession. Thereafter, the video data DV0 is supplied or transmitted to the following circuit through a terminal 87.
A control circuit 86 monitors the capacity of write enable areas of the buffer memory 85 so as to prevent the buffer memory 85 from being overflown with video data DV. This is done to control a data generation parameter frame by frame or multiple frames by multiple frames (for example, 15 frames by 15 frames) so that the amount of data which is generated nearly becomes a constant value because a macro block MB of a non-complicate pattern does not generate a large amount of data, while that of a complicate pattern generates a large amount of data. As an example of the method for monitoring the capacity of the write enable areas, a value of a write address counter and a value of a read address counter in the buffer memory 85 are used. The buffer memory 85, the control circuit 86, and the data generation circuit 84 construct a feed-back loop.
The prior art shown in FIG. 1 had the following problems.
(1) When a picture has partially a complicate pattern, for example, a portion with many edges, the portion causes a large amount of data to be generated. In this case, the feed-back loop constructed of the buffer memory 85, the control circuit 86, and the data generation circuit 84 operates and the control is performed to decrease the amount of data which is generated. However, since the feed-back loop has a delay, when a simple pattern following a complicate pattern is controlled as mentioned above, the picture quality is deteriorated.
(2) Since the control by the feed-back loop constructed of the buffer memory 85, the control circuit 86, and the data generation circuit 84 is always accompanied by a delay, when a large amount of data is abruptly generated as in the case of the above mentioned portion with a complicate pattern, the buffer memory 85 is inevitably overflown.